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SN74LS273DW 데이터시트(PDF) 2 Page - ON Semiconductor |
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SN74LS273DW 데이터시트(HTML) 2 Page - ON Semiconductor |
2 / 8 page SN74LS273 http://onsemi.com 2 18 17 16 15 14 13 12 3 4 5 6 7 20 19 8 VCC MR Q7 D7 D6 Q6 D5 Q5 D4 Q0 D0 D1 Q1 Q2 D2 D3 910 Q3 GND 12 11 Q4 CP CONNECTION DIAGRAM DIP (TOP VIEW) Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs CP D0 – D7 MR Q0 – Q7 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES TRUTH TABLE MR CP Dx Qx L X X L H H H H L L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM CP MR D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q 14 1 26 7 3 8 4 5 9 11 12 13 15 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 17 18 16 19 |
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