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ADC3683 데이터시트(PDF) 46 Page - Texas Instruments |
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ADC3683 데이터시트(HTML) 46 Page - Texas Instruments |
46 / 73 page Figure 8-46. Register 0x08 7 6 5 4 3 2 1 0 0 0 PDN CLKBUF PDN REFAMP 0 PDN A PDN B PDN GLOBAL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 8-15. Register 0x08 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5 PDN CLKBUF R/W 0 Powers down sampling clock buffer 0: Clock buffer enabled 1: Clock buffer powered down 4 PDN REFAMP R/W 0 Powers down internal reference gain amplifier 0: REFAMP enabled 1: REFAMP powered down 3 0 R/W 0 Must write 0 2 PDN B R/W 0 Powers down ADC channel A 0: ADC channel A enabled 1: ADC channel A powered down 1 PDN A R/W 0 Powers down ADC channel B 0: ADC channel B enabled 1: ADC channel B powered down 0 PDN GLOBAL R/W 0 Global power down via SPI 0: Global power disabled 1: Global power down enabled. Power down mask (register 0x0D) determines which internal blocks are powered down. Figure 8-47. Register 0x09 7 6 5 4 3 2 1 0 0 0 PDN FCLKOUT PDN DCLKOUT PDN DA1 PDN DA0 PDN DB1 PDN DB0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 8-16. Register 0x09 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5 PDN FCLKOUT R/W 0 Powers down frame clock (FCLK) LVDS output buffer 0: FCLK output buffer enabled 1: FCLK output buffer powered down 4 PDN DCLKOUT R/W 0 Powers down DCLK LVDS output buffer 0: DCLK output buffer enabled 1: DCLK output buffer powered down 3 PDN DA1 R/W 0 Powers down LVDS output buffer for channel A, lane 1. NOT powered down automatically in 1-wire and 1/2-wire mode. 0: DA1 LVDS output buffer enabled 1: DA1 LVDS output buffer powered down 2 PDN DA0 R/W 0 Powers down LVDS output buffer for channel A, lane 0. 0: DA0 LVDS output buffer enabled 1: DA0 LVDS output buffer powered down 1 PDN DB1 R/W 0 Powers down LVDS output buffer for channel B, lane 1. NOT powered down automatically in 1-wire and 1/2-wire mode. 0: DB1 LVDS output buffer enabled 1: DB1 LVDS output buffer powered down 0 PDN DB0 R/W 0 Powers down LVDS output buffer for channel B, lane 0. NOT powered down automatically in 1/2-wire mode. 0: DB0 LVDS output buffer enabled 1: DB0 LVDS output buffer powered down ADC3683 SBAS872 – DECEMBER 2020 www.ti.com 46 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADC3683 |
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