7 Detailed Description

7.1 Overview

The DLP500YX DMD is a 0.50-inch diagonal spatial light modulator which consists of an array of highly reflective

aluminum micromirrors. The DMD is an electrical input, optical output micro-electrical-mechanical system

(MEMS). The electrical interface is low voltage differential signaling (LVDS). The DMD consists of a two-

dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N

memory cell rows. Refer to the Section 7.2. The positive or negative deflection angle of the micromirrors can be

individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror

reset signals (MBRST).

The DMD is one part of a chipset comprising of the DLP500YX DMD and the DLPC900 Controller. To ensure

reliable operation, the DLPC900 Controller must always be used to control the DLP500YX DMD.

7.2 Functional Block Diagram

Word Lines

Voltages

Control

Channel A Interface

Control

Column Read and Write

Voltage

Generators

Micromirror Array

(0,0)

(M-1, N-1)

Row

Control

Control

Column Read and Write

Channel B Interface

Channels C and D not shown. For pin details on channels A, B, C, and D, refer to the Pin Configurations and Functions table and the

LVDS interface section of Section 6.8.

Figure 7-1. Functional Block Diagram

DLP500YX

DLPS193 – NOVEMBER 2020

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