전자부품 데이터시트 검색엔진 |
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TLV9351 데이터시트(PDF) 39 Page - Texas Instruments |
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TLV9351 데이터시트(HTML) 39 Page - Texas Instruments |
39 / 53 page www.ti.com PACKAGE OUTLINE C TYP 6.6 6.2 1.2 MAX 6X 0.65 8X 0.30 0.19 2X 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max height PW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C A B 5 4 PIN 1 ID AREA SEATING PLANE 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800 |
유사한 부품 번호 - TLV9351_V01 |
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유사한 설명 - TLV9351_V01 |
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