• Voripple is the maximum allowable steady state output voltage ripple

• Iripple is the inductor ripple current

Lastly, if an application does not have a strict load transient response or output ripple requirement, a minimum

amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp setting on

the MODE pin. Equation 12 estimates the minimum capacitance needed for loop stability. This equation sets the

minimum amount of capacitance by keeping the LC frequency relative to the switching frequency at a minimum

value. See Figure 8-3 for the limit versus output voltage with the lowest gain ramp setting of 1 pF. With a 3.3-V

output, the minimum ratio is 25 and with this ratio, Equation 12 gives a minimum capacitance of 5 µF.

2

OUT

SW

OUT

Ratio

1

C

2

f

L

§

·

!

u

¨

¸

S u

©

¹

(12)

Equation 13 calculates the maximum combined ESR the output capacitors can have to meet the output voltage

ripple specification and this shows the ESR should be less than 24 mΩ. In this case, ceramic capacitors are

used and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple.

Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and

failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data

sheet specifies the RMS value of the maximum ripple current. Equation 14 can be used to calculate the RMS

ripple current the output capacitor needs to support. For this application, Equation 14 yields 236 mA and ceramic

capacitors typically have a ripple current rating much higher than this.

Voripple

Resr <

Iripple

(13)

vertical spacer

´

-

´

´

´ ¦

Vout

(Vinm ax

Vout)

Icorm s =

12

Vinm ax

L1

sw

(14)

Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors since they have a high

capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected

with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic

capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website.

For this application example, two 47-µF, 10.0-V, X5R, 0805 ceramic capacitors each with 2 mΩ of ESR are used.

The capacitors are used since they have a higher resonance frequency and can help reduce the output ripple

caused by parasitic inductance. With the two parallel capacitors, the estimated effective output capacitance after

derating using the capacitor manufacturer's website is 98 µF.

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TPS543320

SLUSEE1 – DECEMBER 2020

Copyright © 2020 Texas Instruments Incorporated

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