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DS42585 데이터시트(HTML) 4 Page - Advanced Micro Devices

부품명 DS42585
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Download  58 Pages
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
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DS42585 데이터시트(HTML) 4 Page - Advanced Micro Devices

 
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DS42585
P R E L I M INARY
Key To Switching Waveforms. . . . . . . . . . . . . . . 36
Figure 12. Input Waveforms and Measurement
Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM CE#s Timing . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Timing Diagram for Alternating
Between SRAM to Flash. . . . . . . . . . . . . . . . . . 37
Flash Read-Only Operations . . . . . . . . . . . . . . . . 38
Figure 14. Read Operation Timings . . . . . . . . . 38
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . 39
Figure 15. Reset Timings . . . . . . . . . . . . . . . . . 39
Flash Word/Byte Configuration (CIOf) . . . . . . . . . 40
Figure 16. CIOf Timings for Read Operations . 40
Figure 17. CIOf Timings for Write Operations. . 40
Flash Erase and Program Operations . . . . . . . . . 41
Figure 18. Program Operation Timings. . . . . . . 42
Figure 19. Accelerated Program Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. Chip/Sector Erase Operation
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21. Back-to-back Read/Write Cycle
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. Data# Polling Timings (During
Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 44
Figure 23. Toggle Bit Timings (During
Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 45
Figure 24. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . 45
Temporary Sector/Sector Block Unprotect . . . . . . 46
Figure 25. Temporary Sector/Sector Block
Unprotect Timing Diagram . . . . . . . . . . . . . . . . 46
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram . . . . . . . . . . . . . . . . . 47
Alternate CE#f Controlled Erase and Program
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 27. Flash Alternate CE#f Controlled
Write (Erase/Program) Operation Timings . . . . 49
SRAM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 28. SRAM Read Cycle—Address
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 29. SRAM Read Cycle . . . . . . . . . . . . . . 51
SRAM Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 30. SRAM Write Cycle—WE# Control . . 52
Figure 31. SRAM Write Cycle—CE1#s Control. 53
Figure 32. SRAM Write Cycle—UB#s and
LB#s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash Erase And Programming Performance . . . 55
Flash Latchup Characteristics. . . . . . . . . . . . . . . 55
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 56
Figure 33. CE1#s Controlled Data Retention
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 34. CE2s Controlled Data Retention
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57
FLB073—73-Ball Fine-Pitch Grid Array
8 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision A (May 22, 2001) . . . . . . . . . . . . . . . . . 58


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