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DS42587 데이터시트(PDF) 50 Page - Advanced Micro Devices |
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DS42587 데이터시트(HTML) 50 Page - Advanced Micro Devices |
50 / 58 page 50 DS42587 AC CHARACTERISTICS SRAM Read Cycle Note: CE1#s = OE# = V IL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 28. SRAM Read Cycle—Address Controlled Parameter Symbol Description Min Max Unit t RC Read Cycle Time 85 ns t AA Address Access Time 85 ns t CO1, tCO2 Chip Enable to Output 85 ns t OE Output Enable Access Time 45 ns t BA LB#s, UB#s to Valid Output 85 ns t LZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output 10 ns t BLZ UB#, LB# Enable to Low-Z Output 10 ns t OLZ Output Enable to Low-Z Output 5 ns t HZ1, tHZ2 Chip disable to High-Z Output 0 25 ns t BHZ UB#s, LB#s Disable to High-Z Output 0 25 ns t OHZ Output Disable to High-Z Output 0 25 ns t OH Output Data Hold from Address Change 15 ns ddress ata Out Previous Data Valid Data Valid tAA tRC tOH |
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