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DS42587 데이터시트(HTML) 56 Page - Advanced Micro Devices

부품명 DS42587
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
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DS42587 데이터시트(HTML) 56 Page - Advanced Micro Devices

 
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DS42587
SRAM DATA RETENTION
Note: CE1#s
≥ V
CC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC.
Figure 33.
CE1#s Controlled Data Retention Mode
Figure 34.
CE2s Controlled Data Retention Mode
Parameter
Symbol
Parameter Description
Test Setup
Min
Typ
Max
Unit
V
DR
V
CC for Data Retention
CS1#s
≥ V
CC – 0.2 V (See Note)
1.5
3.3
V
V
DH
Data Retention Current
V
CC = 1.5 V, CE1#s ≥ VCC – 0.2 V
(See Note)
0.5
5
µA
t
SDR
Data Retention Set-Up Time
See data retention waveforms
0ns
tRDR
Recovery Time
tRC
ns
VDR
VCC
2.7V
2.2V
CE1#s
GND
Data Retention Mode
CE1#s
VCC - 0.2 V
tSDR
tRDR
VCC
2.7 V
0.4 V
VDR
CE2s
GND
Data Retention Mode
tSDR
tRDR
CE2s £ 0.2 V


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