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BD9P1X5EFV-C 데이터시트(PDF) 26 Page - Rohm |
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BD9P1X5EFV-C 데이터시트(HTML) 26 Page - Rohm |
26 / 60 page 26/57 TSZ02201-0J1J0AL01480-1-2 © 2019 ROHM Co., Ltd. All rights reserved. 08.Apr.2020 Rev.002 www.rohm.com TSZ22111 • 15 • 001 BD9P1x5EFV-C Series Protect Function - continued 3. Power On Reset (POR)/Under Voltage Lockout Protection (UVLO) The UVLO and POR are integrated to prevent the malfunction when the power supply voltage is decreased. The POR monitors the VIN pin voltage. On the other hand, UVLO monitors the VREG pin voltage. In the sequence of VIN rising, the VREG pin voltage also rises up to 3.3 V (Typ) following VIN voltage. First, UVLO is released when VREG voltage increase above VUVLO_R (2.95 V, Typ). Next, POR is released when VIN voltage increase above VPOR_R (3.8 V, Typ). When both POR and UVLO are released, the IC starts up with soft start. In the sequence of VIN falling, VREG voltage also falls. When VREG voltage decreases below VUVLO_F (2.85 V, Typ), UVLO is detected and puts the IC goes into standby state. At the same time, POR is detected. When the VCC_EX pin is connected to VOUT, VREG voltage supplied from VCC_EX. In this case, drop voltage between VIN and VREG becomes larger than the case of VCC_EX connected to GND because VOUT voltage is restricted by maximum duty at low VIN condition. Therefore, UVLO is detected at higher VIN condition than the case when the VCC_EX pin is connected to GND. VIN VREG VPOR_R VUVLO_F VUVLO_R POR UVLO VOUT 3.8 V (Typ) 2.95 V (Typ) 2.85 V (Typ) 3.3 V (Typ) Figure 42. POR/UVLO Timing Chart |
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