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BD9P1X5EFV-C 데이터시트(PDF) 34 Page - Rohm |
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34 / 60 page 34/57 TSZ02201-0J1J0AL01480-1-2 © 2019 ROHM Co., Ltd. All rights reserved. 08.Apr.2020 Rev.002 www.rohm.com TSZ22111 • 15 • 001 BD9P1x5EFV-C Series Selection of Components Externally Connected - continued 4. Selection of Output Voltage Setting Resistor RFB1, RFB2 (BD9P105EFV-C) For the BD9P105EFV-C, the output voltage is set with external resistors RFB1 and RFB2. The reference voltage of GmAmp1 is set to 0.8 V and the IC operates to regulate FB voltage to 0.8 V. The output voltage is defined by the formula (1). RFB1 and RFB2 should be adjusted to set the required output voltage. If RFB1 and RFB2 are large, the current flowing through on these resistors is small and the circuit current at no load can be reduced. However, the phase shift is likely to happen because of the parasitic capacitance of IC and PCB on the FB pin. Therefore, the combined resistance RFB1//RFB2 should be set to 100 kΩ or less. If the combined resistance RFB1//RFB2 is 100 kΩ or more, CFB1 and CFB2 should be chosen to satisfy the formula (2). In this case, the value of CFB1 and CFB2 should be chose the capacitor of 47 pF or more that is much larger than CP. ���������������� = ������������1+������������2 ������������2 × 0.8 [V] (1) ������������1×������������1 ������������2×������������2 ≈ 1 (2) comp Gm Amp1 0.80 V CP FB VOUT RFB1 RFB2 CFB1 CFB2 Figure 48. Setting for Output Setting Resistor If the voltage between input and output increases and the ON time of the SW decreases to under tONMIN, the switching frequency is decreased. To ensure stable switching frequency, the output voltage must satisfy the following equation. If this equation is not satisfied, the SW pulse is skipped. In this case, the switching frequency decreases and the output voltage ripple increases. ���������������� ≥ ������������(������������) × ������������(������������) × ������������������������(������������) [V] Where: ������������(������������) is the Input Voltage (Max) [V] ������������(������������) is the Switching Frequency (Max) [Hz] (Refer to page 11) ������������������������(������������) is the SW Minimum ON time (Max) [s] (Refer to page 10) If the voltage between input and output decreases, the ON time of the SW increases by skipping the off time and the switching frequency is decreased. To keep switching frequency stably, the following equation must be satisfied. ���������������� ≤ ������������(������������) × (1 − ������������(������������) × ����������������������������(������������)) [V] Where: �����������������������������(������������) is the SW Minimum OFF Time (Max) [s] (Refer to page 10) 5. Selection of the Bootstrap Capacitor For Bootstrap capacitor CBST, please connect a 0.1 μF (Typ) ceramic capacitor as close as possible between the BST pin and the SW pin. 6. Selection of the VREG Capacitor. For VREG capacitor CREG, please connect a 1.0 μF (Typ) ceramic capacitor between the VREG pin and GND. |
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