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BD9P1X5EFV-C 데이터시트(HTML) 4 Page - Rohm

부품명 BD9P1X5EFV-C
상세내용  3.5 V to 40 V Input, 1 A Single 2.2 MHz Buck DC/DC Converter For Automotive
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BD9P1X5EFV-C 데이터시트(HTML) 4 Page - Rohm

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TSZ02201-0J1J0AL01480-1-2
© 2019 ROHM Co., Ltd. All rights reserved.
08.Apr.2020 Rev.002
www.rohm.com
TSZ22111
• 15 • 001
BD9P1x5EFV-C Series
Pin Description
Pin No.
Pin Name
Function
1
EN
Enable pin. Apply low level (0.8 V or lower) to disable device and apply high
level (2.0 V or higher) to enable device. This pin must not be left open.
If this pin is connected to other devices, it is recommended to insert a current
limiting resistor to avoid damages caused by a short between pins.
2
VIN
Power supply input pins for the internal circuit.
Connect this pin to the PVIN pins.
3, 4
PVIN
Power supply input pins that are used for the output stage of the switching
regulator. Connect input ceramic capacitors referring Page 33 between the
PGND pins and these pins.
5
N.C.
This pin is not connected to the chip. Use this as open. If this pin is used other
than open and adjacent pins are expected to be shorted, please confirm if there
is any problem with the actual application.
6, 7
PGND
Ground pins for the output stage of the switching regulator.
8, 9
SW
Switching node pins. These pins are connected to the source of the internal
High Side FET and the drain of the internal Low Side FET. Connect the power
inductor and the bootstrap capacitor.
10
BST
Connect a bootstrap capacitor of 0.1 µF (Typ) between this pin and the SW
pins. The voltage of this capacitor is the gate drive of the High Side FET.
11
OCP_SEL
This is OCP threshold selective pin. OCP threshold is set to 1.250 A (Typ) at
high, and 0.625 A (Typ) at low. These values mean the average inductor
current. Connect this pin to VREG (High) or GND (Low).
12
MODE
Pin to select FPWM (Forced PWM) mode, AUTO (Automatically switched
between PWM mode and LLM) mode, or SYNC (Activate synchronization)
mode. In case of using FPWM mode, set high. In case of using AUTO mode,
set low or open. In case of using SYNC mode, apply a clock to this pin.
13
SSCG
Pin to select Spread Spectrum function. Set high to enable Spread Spectrum
and set low to disable Spread Spectrum. Connect this pin to VREG (High) or
GND (Low).
14
RESET
Output reset pin with open drain. Connect a pull-up resistor to the VREG pin or
the power supply within the absolute maximum voltage ratings of the RESET
pin. Using a 5
kΩ to 100 kΩ resistance is recommended.
15
GND
Ground pin.
16
VOUT_DIS
This pin discharges the VOUT node. Connect this pin to the VOUT when
discharge function is required. Otherwise, connect this pin to GND.
17
(BD9P105EFV-C)
VOUT_SNS
Pin to define the clamp voltage of GmAmp2 output and phase compensation.
Connect this pin to the output voltage.
17
(BD9P135EFV-C,
BD9P155EFV-C)
Inverting input node of the GmAmp1. This pin is used for OVP, SCP and
RESET detection. And, this pin is used for defining the clamp voltage of
GmAmp2 output and phase compensation. Connect this pin to the output
voltage.
18
(BD9P105EFV-C)
FB
Inverting input node of the GmAmp1. This pin is used for OVP, SCP and
RESET detection. Connect output voltage divider to this pin to set the output
voltage.
18
(BD9P135EFV-C,
BD9P155EFV-C)
N.C.
This pin is not connected to the chip. Use this as open. If this pin is used other
than open and adjacent pins are expected to be shorted, please confirm if there
is any problem with the actual application.
19
VCC_EX
This pin is power supply input for internal circuit. VREG voltage is supplied from
VCC_EX when voltage between 3.2 V (VTEXH, Max) and 5.65 V (VEXOVPL, Min) is
connected to this pin. Connecting this pin to VOUT improves efficiency. In case
of not use this function, connect this pin to GND.
20
VREG
Pin to output 3.3 V (Typ) for internal circuit. Connect a ceramic capacitor of 1.0
µF (Typ). Do not connect to any external loads except the OCP_SEL pin, the
MODE pin, the SSCG pin and a pull-up resistor to the RESET pin.
-
EXP-PAD
Exposed pad. The EXP-PAD is connected to the P substrate of the IC. Connect
this pad to the internal PCB ground plane using multiple via holes to obtain
excellent heat dissipation characteristics.


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