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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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BD64008MUV 데이터시트(PDF) 2 Page - Rohm |
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BD64008MUV 데이터시트(HTML) 2 Page - Rohm |
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2 / 39 page  TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 TSZ22111 • 15 • 001 2/36 BD64008MUV © 2017 ROHM Co., Ltd. All rights reserved. www.rohm.com Pin Configuration [TOP VIEW] Block Diagram Pin Description No. Pin Name I/O Function No. Pin Name I/O Function 1 GND - Ground 25 PGNDSW2 - SWREG2 power ground 2 VREFA I H-Bridge A output current setting 26 OUTAM O H-Bridge A output (-) 3 VREFB I Connect to VREFA 27 RNFAS I H-Bridge A current detection input pin 4 SLEEP I Sleep mode setting 28 RNFA O H-Bridge A current detection pin 5 ENBA I H-Bridge A enable input 29 VBBA - H-Bridge A power supply (42 V) 6 ENBB - No function (OPEN or GND) 30 OUTAP O H-Bridge A output (+) 7 CLK I Serial CLK input 31 OUTBP O H-Bridge B output (+) 8 STB(LD) I Serial STB(LD) input 32 VBBB - H-Bridge B power supply (42 V) 9 DAT I Serial DAT input 33 RNFB O H-Bridge B current detection pin 10 ID0 I ID 0 setting 34 RNFBS I H-Bridge B current detection input pin 11 ID1 I ID 1 setting 35 OUTBM O H-Bridge B output (-) 12 ID2 I ID 2 setting 36 GND - Ground 13 ENBSW1 I SWREG1 enable input 37 VBBSW1 - SWREG1 power supply (42 V) 14 ENBSW2 I SWREG2 enable input 38 VBBSW1 - SWREG1 power supply (42 V) 15 PWM I SWREG2 PWM compulsion 39 SWOUT1 O SWREG1 output 16 GND - Ground 40 SWOUT1 O SWREG1 output 17 COMP I/O SWREG2 phase compensation 41 GND - Ground 18 FB2 I SWREG2 feedback 42 FB1 I SWREG1 feedback 19 VINSW2 - SWREG2 power supply (5 V) 43 OCPDET O OCP detection 20 VINSW2 - SWREG2 power supply (5 V) 44 UVDET O VBB drop detection 21 BOOT I SWREG2 H-side Nch booster 45 RESET O Reset out 22 SWOUT2 O SWREG2 output 46 RSTIN I Reset input 23 SWOUT2 O SWREG2 output 47 MODE I Connect to GND 24 PGNDSW2 - SWREG2 power ground 48 UVDETIN I UVDET setting - EXP-PAD - The EXP-PAD is connected to GND. - - - - OUTAP VBBA OUTAM RNFA RNFAS OUTBP VBBB OUTBM RNFB RNFBS LOGIC 4bit DAC (1/5or1/10) RNFAS VREFA 2 VREFB SWOUT1 VBBSW1 PRE DRIVER PRE DRIVER ENBSW1 ENBSW2 PWM GND TSD OCP Clock internal reg. FB1 OSC R S Q DAC for soft start SWOUT2 VINSW2 PRE DRIVER FB2 OSC R S Q DAC for soft start PGNDSW2 BOOT COMP FB1 FB2 OCPDET UVDET RESET UVDETIN UVP MODE internal reg. Regulator 3 47 17 48 16 36 1 41 SLEEP ENBA,ENBB CLK,STB(LD),DAT ID0,ID1,ID2 RSTIN 4 to 12 29 30 26 28 27 32 31 35 33 34 37 38 39 40 42 21 19 20 22 23 24 25 18 43 44 45 46 14 15 13 10 10 3 3 Internal reg. 23 RESET UVDET SWOUT1 SWOUT1 1 2 3 4 5 6 7 RSTIN UVDETIN 24 13 14 15 16 17 25 36 35 34 33 40 39 38 37 48 47 46 SWOUT2 VINSW2 VINSW2 FB2 GND PWM OCPDET VBBSW1 VBBSW1 9 10 8 18 19 20 SWOUT2 30 29 28 27 26 MODE ENBSW1 ENBSW2 45 44 43 PGNDSW2 12 21 22 FB1 GND 42 41 11 32 31 COMP BOOT EXP-PAD |
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