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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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BM81810MUF-M 데이터시트(PDF) 39 Page - Rohm |
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BM81810MUF-M 데이터시트(HTML) 39 Page - Rohm |
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39 / 78 page  BM81810MUF-M . 39/75 TSZ02201-0A3A0AS00510-1-2 © 2020 ROHM Co., Ltd. All rights reserved. 15.May.2020 Rev.001 TSZ22111 • 15 • 001 www.rohm.com EEPROM Parameter Setting When Start-up bit(REG0Ch[7]) is ”1”, below Register cannot be modified. VGH NTC Enable REG02h[7] VCOM NTC Enable REG05h[7] VDD mode select REG06h[6] Function select REG08h[7] VGH mode select REG0Ch[6] To change those Register setting, start-up bit(REG0Ch[7]) should be in ”0”. After changing the register value, set the Start-up bit(REG0Ch[7]) to “1” again to start up with the changed setting. Device Address: 1001111x (VCOM) Register Address Bits Function Resolution Comments - 7 VCOM Calibrator +/- 0.01V [ VCOM +/- 0.63V] VCOM Calibrator ■EEPRO M / Main Re giste r Map ( de vic e addre ss : 1 0 0 0 0 0 0 x ) Device Address: 1000000x (PMIC) Regis ter Addres s Bits Function Res olution Com m ents Δ VGH(COLD) Voltage [6:0] 0.2V [VGH(HOT) + 15V] VGH NTC Enalbe [7] 0:Dis able, 1:Enable Δ VCOM(COLD) Voltage [6:0] 10m V [VCOM(HOT) - 0.63V] VCOM NTC Enalbe [7] 0:Dis able, 1:Enable VDD Output voltage [5:0] 0.05V [0.9V to 3.4V] VDD Output voltage s etting VDD m ode s elect [6] 0 : DC/DC, 1 : LDO Select VDD operation mode DC/DC or LDO VDD Phas e [7] See P.56 page. s elect VDD Phas e Res et Voltage [4:0] 0.1V [0.6V to 3.3V] Res et voltage s etting Res et m onitor s elect [5] 0:VDD, 1:VIN Select m onitor pin of res et function GPM input delay [7:6] 00: 0.1usec, 01: 0.5usec, 10: 1.0usec, 11: 1.5usec GPM input propagation delay tim e s etting Dis charge tim e [2:0] 1m s ec [0 to 5m s ec] Pre-dis charge tim e s etting Delay1 tim e [6:3] [0 to 300m s ec] Load sw itch of AVDD start-up delay time setting Function Select [7] 0: PG, 1: LDSW 24pin function s elect Delay2 tim e [2:0] 5m s ec [0 to 30m s ec, 40m s ec] Res et s tart delay tim e s etting DoubleReg [3] 0: Dis able, 1: Enable Double Regis ter Function Delay3 tim e [6:4] 5m s ec [0 to 30m s ec, 40m s ec] VGL or VGH s tart-up delay tim e s etting DataRef [7] 0: Dis able, 1: Enable Data Refres h Function Delay4 tim e [2:0] 5m s ec [0 to 30m s ec, 40m s ec] GPM s tart delay tim e s etting AR_Tim e [3] 0: 0.5s ec, 1: 1.0s ec Data Refres h Tim e Delay5 tim e [6:4] 2m s ec [0 to 10m s ec] VDD s top delay tim e s etting VGH Dis charge enable [7] 0: Enable, 1: Dis able VGH Dis charge function enable AVDD Coil[1:0] See p.49 page. s elect AVDD Coil indactance AVDD SW Slew Rate [3:2] See p.48 page. 4s tep s lew rate s etting (11:fas t → 00:s low) AVDD SS tim e [5:4] 5m s ec [5m s ec to 20m s ec] AVDD s ofts tart tim e s etting AVDD OCP Select [6] 0: 2A, 1: 1A AVDD OCP m in value s elect AVDD COMP [7] See p.49 page. AVDD phas e com pens ation s etting AVDD Frequecy [1:0] 00:2.1MHz, 01:1.05MHz, 10:525KHz, 11:525KHz Seletc AVDD s witching frequency VDD Frequecy [3:2] 00:2.1MHz, 01:1.05MHz, 10:525KHz, 11:525KHz Select VDD s witching frequency VGH / VGL Frequecy [5:4] AVDD Freqency ( 00: x1, 01: --, 10: --, 11: -- ) Select VGH and VGL s witching frequency. Choose only "00". VGH m ode s elect [6] 0: x3 m ode, 1: x2 or x4 m ode Select VGH charge pum p m ode s tart-up bit [7] 0:Dis able, 1:Enable 0Bh 8 0Ch 8 08h 8 09h 8 0Ah 8 05h 8 06h 8 07h 8 VGL Output voltage s etting 04h 8 VCOM(HOT) Output voltage 40m V [0.5xAVDD ±4.0V] VCOM(HOT) Output voltage s etting 0.1V [-14.0V to -4.0V] 02h 8 03h 8 VGL Output voltage 00h 8 AVDD Output voltage 0.1V [5.0V to 17.0V] AVDD Output voltage s etting 01h 8 VGH(HOT) Output voltage 0.2V [8.0V to 35.0V] VGH(HOT) Output voltage s etting |
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