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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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BM81810MUF-M 데이터시트(PDF) 65 Page - Rohm |
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BM81810MUF-M 데이터시트(HTML) 65 Page - Rohm |
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65 / 78 page  BM81810MUF-M . 65/75 TSZ02201-0A3A0AS00510-1-2 © 2020 ROHM Co., Ltd. All rights reserved. 15.May.2020 Rev.001 TSZ22111 • 15 • 001 www.rohm.com Double Register BM81810MUF-M can perform various setting by Register. If these settings are changed without intension, to avoid application abnormal operation, certain specific Register has error detection function. Below shows the Register with anomaly detection function. Double Register correspond BIT Data Refresh Data Refresh is the Function to read Data from EEPROM periodically. If Register setting is suddenly changed without intension, Data Refresh function can read Data from EEPROM to recover to the normal Data. Data Refresh performs at certain cycle period. The time of period can be set by Register at 0.5s or 1.0s. In the case of WPN=Low, Double Register Function and Data Refresh Function can be set by Register as Enable or Disable. Below table shows the function by each combination. In the case of WPN=High, Double Register Function and Data Refresh Function are Disable. Enable （First shutdown once logic abnormality detects. After Fault to be low for 1msec, then re-start） Disable （Keep working even logic abnormality happens） Enable (Perform Data Refresh once logic abnormality detects) Disable （Keep working even logic abnormality happens） Enable （Data Refresh at set period） Enable （Data Refresh at set period） WPN Data Refresh Operation Double Register Check Low 0 : Disable 0 : Disable Disable Data Refresh Double Register Disable （Keep working even logic abnormality happens） High - - Disable 1 : Enable Disable Low 1 : Enable 0 : Disable Low 1 : Enable 1 : Enable Low 0 : Disable Register Address D7 D6 D5 D4 D3 D2 D1 D0 00h 01h 02h VGH NTC Enable 03h 04h 05h VCOM NTC Enable 06h VDD Phase VDD MODE 07h Reset Monitor Select 08h Function Select 09h Data Refresh DoubleReg 0Ah VGH Discharge Enable AR_Time 0Bh AVDD COMP AVDD OCP Select 0Ch Start-up Bit VGH mode select 0Dh 10h AVDD UVP VDD UVP VGH UVP VGL UVP Double Register Error AVDD OCP TSD Check sum Error AVDD Output Voltage VGH HOT Output Voltage ⊿VGH COLD Voltage VGL Output Voltage VCOM HOT Output Voltage VCOM COLD Votlage Delay3 time Delay2 time VDD Output Voltage GPM Input Delay Reset Voltage Delay1 time Discharge time Check Sum Delayt5 time AVDD SS Time AVDD SW Slew Rate AVDD COIL VGH/VGL Frequency VDD Frequency AVDD Frequency Delay4 time |
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