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KM68V257C 데이터시트(PDF) 4 Page - Samsung semiconductor |
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KM68V257C 데이터시트(HTML) 4 Page - Samsung semiconductor |
4 / 9 page KM68V257C CMOS SRAM PRELIMINARY Rev 3.0 - 4 - February 1998 TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below AC CHARACTERISTICS(TA=0 to 70 °C, VCC=3.3±0.3V, unless otherwise noted.) Output Loads(B) DOUT 5pF* 319 Ω 353 Ω for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V READ CYCLE Parameter Symbol KM68V257C-15 KM68V257C-17 Unit Min Max Min Max Read Cycle Time tRC 15 - 17 - ns Address Access Time tAA - 15 - 17 ns Chip Select to Output tCO - 15 - 17 ns Output Enable to Valid Output tOE - 7 - 8 ns Chip Enable to Low-Z Output tLZ 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 7 0 8 ns Output Disable to High-Z Output tOHZ 0 7 0 8 ns Output Hold from Address Change tOH 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - ns Chip Selection to Power DownTime tPD - 15 - 17 ns * Including Scope and Jig Capacitance Output Loads(A) DOUT RL = 50 Ω ZO = 50 Ω VL = 1.5V 30pF* * Capacitive Load consists of all components of the test environment. |
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