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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 35 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TH58NS100DC
์ƒ์„ธ๋‚ด์šฉ  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )
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์ œ์กฐ์‚ฌ  TOSHIBA [Toshiba Semiconductor]
ํ™ˆํŽ˜์ด์ง€  http://www.semicon.toshiba.co.jp/eng
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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 35 Page - Toshiba Semiconductor

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TH58NS100DC
2001-03-21
35/43
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
(7)
Status Read during a Read operation
The device status can be read out by inputting the Status Read command โ€œ70Hโ€ in Read mode.
Once the device has been set to Status Read mode by a โ€œ70Hโ€ command, the device will not return to Read
mode.
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command โ€œ00Hโ€ is input during [A], Status mode is reset and the device returns
to Read mode. In this case, data output starts automatically from address N and address input is
unnecessary
DATA IN: Data (1)
Page 0
Data register
Page 2
Page 1
Page 15
Page 31
(1)
(2)
(3)
(16)
(32)
Data (32)
From the LSB page to MSB page
DATA IN: Data (1)
Page 0
Data register
Page 2
Page 1
Page 15
Page 31
(2)
(16)
(3)
(1)
(32)
Data (32)
Ex.) Random page program (Prohibition)
Figure 17. page programming within a block
00
Address N
command
CE
WE
BY
/
RY
RE
[A]
Status Read
command input
Status Read
Status output
Figure 18.
70
00


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