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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 40 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TH58NS100DC
์ƒ์„ธ๋‚ด์šฉ  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )
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์ œ์กฐ์‚ฌ  TOSHIBA [Toshiba Semiconductor]
ํ™ˆํŽ˜์ด์ง€  http://www.semicon.toshiba.co.jp/eng
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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 40 Page - Toshiba Semiconductor

 
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TH58NS100DC
2001-03-21
40/43
(12)
Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:
(13)
Note regarding the RE signal
RE
The internal column address counter is incremented synchronously with the RE clock in Read
mode. Therefore, once the device has been set to Read mode by a โ€œ00Hโ€, โ€œ01Hโ€ or โ€œ50Hโ€ command, the
internal column address counter is incremented by the RE clock independently of the address input timing,
If the RE clock input pulses start before the address input, and the pointer reaches the last column
address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer
to Figure 25.)
Hence the RE clock input must start after the address input.
Data Pattern 3
Data Pattern 1
All 1s
Figure 24.
1st programming
2nd programming
nth programming
Result
Data Pattern 1
Data Pattern 3
Data Pattern 2
All 1s
Data Pattern 2
All 1s
Note: The input data for unprogrammed or previously programmed page segments must be โ€œ1โ€
(i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all โ€œ1โ€).
All 1s
Figure 25.
Address input
WE
I/O
BY
/
RY
RE
00H/01H/50H


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