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TH58NS100DC 데이터시트(HTML) 5 Page - Toshiba Semiconductor

부품명 TH58NS100DC
상세내용  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )
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제조사  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TH58NS100DC 데이터시트(HTML) 5 Page - Toshiba Semiconductor

 
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TH58NS100DC
2001-03-21
5/43
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the
BY
/
RY
pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE
delay is less than 30 ns,
BY
/
RY
signal stays Ready.
PROGRAMMING AND ERASING CHARACTERISTICS (Ta
==== 0° to 55°C, VCC ==== 3.3 V ±±±± 0.3 V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NOTES
tPROG
Programming Time
¾
200
1000
ms
tDBSY
Dummy Busy Time for Multi Block
Programming
¾
2
10
ms
tMBPBSY
Multi Block Program Busy Time
¾
200
1000
ms
N
Number of Programming Cycles on Same
Page
¾
¾
3
(1)
tBERASE
Block Erasing Time
¾
2
10
ms
(1): Refer to Application Note (12) toward the end of this document.
: 0 to 30 ns
® Busy signal is not output.
A
CE
RE
tCEH ³ 100 ns
*
525
Busy
BY
/
RY
*: VIH or VIL
A
526
527
tCRY


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