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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 21 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TH58NS100DC
์ƒ์„ธ๋‚ด์šฉ  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )
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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 21 Page - Toshiba Semiconductor

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TH58NS100DC
2001-03-21
21/43
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
A page consists of 528 bytes in which 512 bytes are used for
main memory storage and 16 bytes are for redundancy or
for other uses.
1 page = 528 bytes
1 block = 528 bytes ยด 32 pages = (16K + 512) bytes
Capacity = 528 bytes ยด 32 pages ยด 8192 blocks
An address is read in via the I/O port over four
consecutive clock cycles, as shown in Table 1.
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
First cycle
A7
A6
A5
A4
A3
A2
A1
A0
Second cycle
A16
A15
A14
A13
A12
A11
A10
A9
Third cycle
A24
A23
A22
A21
A20
A19
A18
A17
Fourth cycle
*L
*L
*L
*L
*L
*L
A26
A25
A0 to A7
: Column address
A9 to A26 : Page address
A14 to A26 : Block address
A9 to A13 : NAND address in block
* : A8 is automatically set to Low or High by a 00H command or a 01H command.
* : l/O3 to l/O8 must be set to Low in the fourth cycle.
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the fourteen different
command operations shown in Table 3. Address input, command input and data input/output are controlled by
the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
WE
RE
WP
Command Input
H
L
L
H
*
Data Input
L
L
L
H
*
Address Input
L
H
L
H
*
Serial Data Output
L
L
L
H
*
During Programming (Busy)
*
*
*
*
*
H
During Erasing (Busy)
*
*
*
*
*
H
Program, Erase Inhibit
*
*
*
*
*
L
H: VIH, L: VIL, *: VIH or VIL
16
512
I/O1
I/O8
8I/O
528
262144 pages
8192 blocks
Figure 2. Schematic Cell Layout
32 pages
1 block


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