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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 23 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TH58NS100DC
์ƒ์„ธ๋‚ด์šฉ  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )
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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 23 Page - Toshiba Semiconductor

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TH58NS100DC
2001-03-21
23/43
DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a โ€œ00Hโ€ command is issued to the Command register. Refer to Figure 3 below for
timing details and the block diagram.
Read Mode (2)
BY
/
RY
WE
CLE
RE
M
N
Start-address
input
00H
CE
ALE
I/O
Cell array
Select page
N
M
Figure 3. Read mode (1) operation
527
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the fourth cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period. The CE signal must
stay Low after the fourth address input and during Busy state.
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
Busy
BY
/
RY
WE
CLE
RE
M
N
Start-address
input
01H
CE
ALE
I/O
Cell array
Select page
N
M
Figure 4. Read mode (2) operation
527
The operation of the device after input of the 01H command is
the same as that of Read mode (1). If the start pointer is to be
set after column address 256, use Read mode (2).
However, for a Sequential Read, output of the next page
starts from column address 0.
Busy
256


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