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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 24 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TH58NS100DC
์ƒ์„ธ๋‚ด์šฉ  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )
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์ œ์กฐ์‚ฌ  TOSHIBA [Toshiba Semiconductor]
ํ™ˆํŽ˜์ด์ง€  http://www.semicon.toshiba.co.jp/eng
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TH58NS100DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 24 Page - Toshiba Semiconductor

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TH58NS100DC
2001-03-21
24/43
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte
527.
Sequential Read (1) (2) (3)
This mode allows the sequential reading of pages without additional address input.
Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential
Read mode (3) outputs the contents of the redundant address locations only.
When the page address reaches the next block address, read command (00H/01H/50H) and address inputs are
needed.
BY
/
RY
WE
CLE
RE
50H
CE
ALE
I/O
Figure 5. Read mode (3) operation
527
Addresses bits A0 to A3 are used to set the start pointer for
the redundant memory cells, while A4 to A7 are ignored.
Once a โ€œ50Hโ€ command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4-to-A7 address.
(A โ€œ00Hโ€ command is necessary to move the pointer back to
the 0-to-511 main memory cell location.)
512
A0 to
A3
Busy
00H
Busy
01H
Busy
Busy
Address input
tR
Data output
50H
A
Sequential Read (1)
(00H)
0
527
A
Sequential Read (3)
(50H)
512 527
Data output
tR
tR
A
Sequential Read (2)
(01H)
527
256
BY
/
RY


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