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AM50DL128CG 데이터시트(HTML) 43 Page - SPANSION

부품명 AM50DL128CG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM50DL128CG 데이터시트(HTML) 43 Page - SPANSION

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Am50DL128CG
November 7, 2002
P R E L I M I NARY
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Note: CE#f refers to the flash device being reset (either CE#f1 or CE#f2).
Figure 16.
Reset Timings
Parameter
Description
All Speed Options
Unit
JEDEC
Std
t
Ready
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
µs
t
Ready
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
t
RP
RESET# Pulse Width
Min
500
ns
t
RH
Reset High Time Before Read (See Note)
Min
50
ns
t
RPD
RESET# Low to Standby Mode
Min
20
µs
t
RB
RY/BY# Recovery Time
Min
0
ns
RESET#1,
RESET#2
RY/BY#1,
RY/BY#2
RY/BY#1,
RY/BY#2
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#f, OE#
tRH
CE#f, OE#
Reset Timings during Embedded Algorithms
RESET#1,
RESET#2
tRP
tRB


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