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AM50DL128CG 데이터시트(HTML) 44 Page - SPANSION

부품명 AM50DL128CG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM50DL128CG 데이터시트(HTML) 44 Page - SPANSION

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November 7, 2002
Am50DL128CG
43
P R E L I M I NARY
FLASH AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
3. CE#f refers to chip enable input of active flash (device being addressed).
Parameter
Speed
JEDEC
Std
Description
70
85
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
70
85
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
40
45
ns
t
AHT
Address Hold Time From CE#f or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
40
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time (CE#f to WE#)
Min
0
ns
t
ELWL
t
CS
CE#f Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time (CE#f to WE#)
Min
0
ns
t
WHEH
t
CH
CE#f Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
30
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Word
Typ
7
µs
t
WHWH1
t
WHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
4
µs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.4
sec
t
VCS
V
CC Setup Time (Note 1)
Min
50
µs
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns


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