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AM50DL128CG 데이터시트(HTML) 48 Page - SPANSION

부품명 AM50DL128CG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM50DL128CG 데이터시트(HTML) 48 Page - SPANSION

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November 7, 2002
Am50DL128CG
47
P R E L I M I NARY
FLASH AC CHARACTERISTICS
OE#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read)
(second read)
(stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2
Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
CE#f
Note:
1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
2. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash
device must be held high during this operation.
Figure 22.
Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 23.
DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing


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