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AM50DL128CG 데이터시트(HTML) 52 Page - SPANSION

부품명 AM50DL128CG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM50DL128CG 데이터시트(HTML) 52 Page - SPANSION

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November 7, 2002
Am50DL128CG
51
P R E L I M I NARY
FLASH AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#f
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7#
DOUT
tWC
tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SADD for sector erase
555 for chip erase
tBUSY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
OUT is the data written to the device.
4. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must
be held high during this operation.
5. Waveforms are for the word mode.
Figure 26.
Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings


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