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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM50DL128CG 데이터시트(HTML) 53 Page - SPANSION |
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AM50DL128CG 데이터시트(HTML) 53 Page - SPANSION |
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52 Am50DL128CG November 7, 2002 P R E L I M I NARY pSRAM AC CHARACTERISTICS Read Cycle Notes: 1. t OD, tODo, tBD, and tODW are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. If CE#, LB#, or UB# goes low at the same time or before WE# goes high, the outputs will remain at high impedance. 3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. Figure 27. Pseudo SRAM Read Cycle Parameter Symbol Description Speed Unit 70 85 t RC Read Cycle Time Min 70 85 ns t ACC Address Access Time Max 70 85 ns t CO Chip Enable Access Time Max 70 85 ns t OE Output Enable Access Time Max 25 ns t BA Data Byte Control Access Time Max 25 ns t COE Chip Enable Low to Output Active Min 10 ns t OEE Output Enable Low to Output Active Min 0 ns t BE Data Byte Control Low to Output Active Min 0 ns t OD Chip Enable High to Output High-Z Max 20 ns t ODO Output Enable High to Output High-Z Max 20 ns t BD Data Byte Control High to Output High-Z Max 20 ns t OH Output Data Hold from Address Change Min 10 ns t PM Page Mode Time Min 70 ns t PC Page Mode Cycle Time Min 30 ns t AA Page Mode Address Access Time Max 30 ns t AOH Page Output Data Hold Time Min 10 ns tRC tACC Addresses A20 to A0 CE#1 CE2 OE# WE# LB#, UB# DOUT DQ15 to DQ0 tCO tOH Fixed High High-Z High-Z tOE tBA tOD tODO tBD Valid Data Out Indeterminate tBE tOEE tCOE |
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