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AM50DL128CG 데이터시트(HTML) 9 Page - SPANSION

부품명 AM50DL128CG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Download  63 Pages
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제조사  SPANSION [SPANSION]
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AM50DL128CG 데이터시트(HTML) 9 Page - SPANSION

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Am50DL128CG
November 7, 2002
P R E L I M I NARY
PIN DESCRIPTION
A21–A0
= 22 Address Inputs (Common)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash 1)
CE#f2
= Chip Enable 2 (Flash 2)
CE1#ps
= Chip Enable 1 (pSRAM)
CE2ps
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#1
= Ready/Busy Output (Flash 1)
RY/BY#2
= Ready/Busy Output (Flash 2)
UB#
= Upper Byte Control (pSRAM)
LB#
= Lower Byte Control (pSRAM)
RESET#1
= Hardware Reset Pin, Active Low
(Flash 1)
RESET#2
= Hardware Reset Pin, Active Low
(Flash 2)
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CCps
= pSRAM Power Supply
V
SS
= Device Ground (Common)
NC
= Pin Not Connected Internally
LOGIC SYMBOL
22
16
DQ15–DQ0
A21–A0
CE#f1
OE#
WE#
RESET#1
UB#
RY/BY#1
WP#/ACC
LB#
CE1#ps
CE2ps
CE#f2
RESET#2
RY/BY#2


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