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AM50DL128CG 데이터시트(HTML) 14 Page - SPANSION

부품명 AM50DL128CG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM50DL128CG 데이터시트(HTML) 14 Page - SPANSION

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November 7, 2002
Am50DL128CG
13
P R E L I M I NARY
(Note that this is a more restricted voltage range than
V
IH.) If CE#f and RESET# are held at VIH, but not
within V
CC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (t
CE) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until th e
operation is completed.
I
CC3f in the table represents the standby current spec-
ification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC +
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5f in the table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS±0.3 V, the device
draws CMOS standby current (I
CC4f). If RESET# is
held at V
IL but not within VSS±0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY (during Embedded Algorithms). The
system can th us monito r RY/BY# to de termin e
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
READY (not during Embedded
Algorithms). The system can read data t
RH after the
RESET# pin returns to V
IH.
Refer to the pSRAM AC Characteristics tables for RE-
SET# parameters and to Figure 16 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
IH, output from the device is
disabled. The output pins are placed in the high
impedance state.


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