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AD9216BCPZ-105 데이터시트(PDF) 3 Page - Analog Devices

부품명 AD9216BCPZ-105
상세설명  10-Bit, 65/80/105 MSPS Dual A/D Converter
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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AD9216BCPZ-105 데이터시트(HTML) 3 Page - Analog Devices

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Preliminary Technical Data
AD9216
Rev. PrD
Page 3 of 20
6/15/2004
AD9216–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Test
AD9216BCP-65/80
AD9216BCP-105
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
VI
10
10
Bits
ACCURACY
No Missing Codes Guaranteed
Full
VI
10
10
Bits
Offset Error
Full
VI
±0.3
±TBD
±0.30
±TBD
% FSR
Gain Error
1
Full
IV
±1.0
±TBD
±1.0
±TBD
% FSR
Differential Nonlinearity (DNL)
2
Full
V
±0.5
±0.5
LSB
25°C
I
±0.5
±TBD
±0.5
±TBD
LSB
Integral Nonlinearity (INL)
2
Full
V
±0.5
±0.5
LSB
25°C
I
±0.5
±TBD
±0.5
±TBD
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
±15
±15
ppm/°C
Gain Error
1
Full
V
±30
±30
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
VI
±5
±35
±5
±35
mV
Load Regulation @ 1.0 mA
Full
V
0.8
0.8
mV
Output Voltage Error (0.5 V Mode)
Full
V
±2.5
±2.5
mV
Load Regulation @ 0.5 mA
Full
V
0.1
0.1
mV
INPUT REFERRED NOISE
Input Span = 1 V
25°C
V
0.8
0.8
LSB rms
Input Span = 2.0 V
25°C
V
0.4
0.4
LSB rms
ANALOG INPUT
Input Span = 1.0 V
Full
IV
1
1
V p-p
Input Span = 2.0 V
Full
IV
2
2
V p-p
Input Capacitance
3
Full
V
2
2
pF
REFERENCE INPUT RESISTANCE
Full
V
7
7
k?
POWER SUPPLIES
Supply Voltages
AVDD
Full
IV
2.7
3.0
3.3
2.7
3.0
3.3
V
DRVDD
Full
IV
2.25
2.5
3.6
2.25
2.5
3.6
V
Supply Current
IAVDD
2
Full
V
TBD/TBD
TBD
mA
IDRVDD
2
Full
V
TBD/TBD
TBD
mA
PSRR
Full
V
±0.01
±0.01
% FSR
POWER CONSUMPTION
DC Input
4
Full
V
TBD/TBD
TBD
mW
Sine Wave Input
2
Full
VI
215/238
280
mW
Standby Power
5
Full
V
1/1
1
mW
MATCHING CHARACTERISTICS
Offset Error
Full
V
±0.1
±0.1
% FSR
Gain Error
Full
V
±0.05
±0.05
% FSR
1 Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure xx for the equivalent analog input
structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.


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