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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Z8F3221VN020SC 데이터시트(PDF) 86 Page - Zilog, Inc. |
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Z8F3221VN020SC 데이터시트(HTML) 86 Page - Zilog, Inc. |
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86 / 299 page  PS019915-1005 Interrupt Controller Z8 Encore!® 64K Series Product Specification 66 The following style of coding to generate software interrupts by setting bits in the Interrupt Request registers is NOT recommended. All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 To avoid missing interrupts, the following style of coding to set bits in the Interrupt Request registers is recommended: Good coding style that avoids lost interrupt requests: ORX IRQ0, MASK Interrupt Control Register Definitions For all interrupts other than the Watch-Dog Timer interrupt, the interrupt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests. Interrupt Request 0 Register The Interrupt Request 0 (IRQ0) register (Table 24) stores the interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec- tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 0 register to determine if any interrupt requests are pending Table 24. Interrupt Request 0 Register (IRQ0) BITS 7 6 5 4 3 2 1 0 FIELD T2I T1I T0I U0RXI U0TXI I2CI SPII ADCI RESET 0 R/W R/W ADDR FC0H Caution: |
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