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Z8F3222VS020EC 데이터시트(PDF) 84 Page - Zilog, Inc. |
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Z8F3222VS020EC 데이터시트(HTML) 84 Page - Zilog, Inc. |
84 / 299 page PS019915-1005 Interrupt Controller Z8 Encore!® 64K Series Product Specification 64 Architecture Figure 11 illustrates a block diagram of the interrupt controller. Figure 11. Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions: • Executing an EI (Enable Interrupt) instruction • Executing an IRET (Return from Interrupt) instruction • Writing a 1 to the IRQE bit in the Interrupt Control register Interrupts are globally disabled by any of the following actions: • Execution of a DI (Disable Interrupt) instruction • eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller • Writing a 0 to the IRQE bit in the Interrupt Control register • Reset Vector IRQ Request High Priority Medium Priority Low Priority Priority Mux Port Interrupts Internal Interrupts |
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