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Z8F3221PM020AC 데이터시트(PDF) 12 Page - Zilog, Inc. |
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Z8F3221PM020AC 데이터시트(HTML) 12 Page - Zilog, Inc. |
12 / 299 page PS019915-1005 List of Figures Z8 Encore!® 64K Series Product Specification xii Figure 33. Receive Data Format for a 10-Bit Addressed Slave . . . . . . . . . . . . . . . . . 150 Figure 34. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 172 Figure 35. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Figure 36. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 37. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 39. OCD Data Format 196 Figure 40. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 206 Figure 41. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 207 Figure 42. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kW Resistor . . . . . . . . . . . . . . . . . . . . . . . 208 Figure 43. Typical Active Mode Idd Versus System Clock Frequency . . . . . . . . . . . 213 Figure 44. Maximum Active Mode Idd Versus System Clock Frequency . . . . . . . . . 214 Figure 45. Typical HALT Mode Idd Versus System Clock Frequency . . . . . . . . . . . 215 Figure 46. Maximum HALT Mode Icc Versus System Clock Frequency . . . . . . . . . 216 Figure 47. Maximum STOP Mode Idd with VBO enabled versus Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 48. Maximum STOP Mode Idd with VBO Disabled versus Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 49. Analog-to-Digital Converter Frequency Response . . . . . . . . . . . . . . . . . . 223 Figure 50. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 51. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 52. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 53. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Figure 54. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Figure 55. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 56. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Figure 57. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Figure 58. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Figure 59. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Figure 60. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Figure 61. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Figure 62. 40-Lead Plastic Dual-Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . 257 Figure 63. 44-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . . . . . . . . . 258 Figure 64. 44-Lead Plastic Lead Chip Carrier Package (PLCC) . . . . . . . . . . . . . . . . 259 |
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