SMM665B

Preliminary Information

Summit Microelectronics, Inc

2089 1.1 10/20/04

11

Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.

See Figure 4 Timing Diagram.

100kHz

400kHz

Symbol

Description

Conditions

Min

Typ

Max

Min

Typ

Max

Units

SCL Clock Frequency

0

100

0

400

KHz

Clock Low Period

4.7

1.3

µs

Clock High Period

4.0

0.6

µs

Bus Free Time

Before New Transmission

4.7

1.3

µs

Start Condition Setup

Time

4.7

0.6

µs

Start Condition Hold Time

4.0

0.6

µs

Stop Condition Setup Time

4.7

0.6

µs

Clock Edge to Data Valid

SCL low to valid

SDA (cycle n)

0.2

3.5

0.2

0.9

µs

Data Output Hold Time

SCL low (cycle n+1)

to SDA change

0.2

0.2

µs

SCL and SDA Rise Time

Note 1/

1000

1000

ns

SCL and SDA Fall Time

Note 1/

300

300

ns

Data In Setup Time

250

150

ns

Data In Hold Time

0

0

ns

TI

Noise Filter SCL and SDA

Noise suppression

100

100

ns

Configuration

Registers

10

10

ms

Write Cycle Time EE

Memory Array

5

5

ms

Note: 1/ - Guaranteed by Design.

t

R

t

F

t

HIGH

t

LOW

t

SU:SDA

t

HD:SDA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

BUF

t

DH

t

AA

SCL

SDA

(IN)

SDA

(OUT)

t

W R (For W rite Operation Only)

Figure 4 - Basic I

TIMING DIAGRAMS