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SMM764FR2 데이터시트(PDF) 11 Page - Summit Microelectronics, Inc.

부품명 SMM764FR2
상세설명  Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link?
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제조업체  SUMMIT [Summit Microelectronics, Inc.]
홈페이지  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

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SMM764
Preliminary Information
Summit Microelectronics, Inc
2098 1.1 6/29/2005
11
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 5
and 6 Timing diagrams.
Symbol
Description
Conditions
Min
Typ
Max
Unit
tDPON = 0.64ms
tDPON = 12.5ms
tDPON = 25ms
tDPON
Programmable power-on delay
from restart timer expiration to
PUPX active.
tDPON = 50ms
-25
tDPON
+25
%
tDPOFF = 0.64ms
tDPOFF
Programmable power-off delay
from VMX off to PUPX inactive
tDPOFF = 12.5ms
-25
tDPOFF
+25
%
tPRTO = 0.64ms
tPRTO = 25ms
tPRTO = 100ms
tPRTO
Programmable reset time-out delay
tPRTO = 200ms
-25
tPRTO
+25
%
tSTT = OFF
tSTT = 100ms
tSTT = 200ms
tSTT
Programmable sequence
termination timer
tSTT = 400ms
-25
tSTT
+25
%
tFTRD
Fault-triggered restart delay
Time from restart timer
expiration to PUPX active
after a fault-triggered power-
off or force-shutdown.
2.4
s
tFTRDACC
Fault-triggered restart delay
accuracy
-25
tFTRD
+25
%
tCTRD
Command-triggered restart delay
Time from restart timer
expiration to PUPX active
after command-triggered
power-off or force-shutdown.
12.5
ms
tCTRDACC
Command-triggered restart delay
accuracy
-25
tCTRD
+25
%
TADC
10-bit ADC sampling period
Time for ADC conversion of
all 9 channels
2.0
ms
TDC_CONTROL
ADOC sampling period
Update period for ADOC of
channels
A – D
1.7
ms
Slow Margin, + 10% change
in voltage with 0.1% ripple
TRIM_CAP=1
µF
850
ms
tMARGIN
Margin Time from Nominal
Fast Margin, + 10% change
in voltage with 0.1% ripple
TRIM_CAP=1
µF
85
ms
AC OPERATING CHARICTERISTICS


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