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SMS45GR00 데이터시트(PDF) 2 Page - Summit Microelectronics, Inc. |
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SMS45GR00 데이터시트(HTML) 2 Page - Summit Microelectronics, Inc. |
2 / 20 page 2 SMS45 2079 1.2 05/24/04 SUMMIT MICROELECTRONICS, Inc. Preliminary Information INTERNAL BLOCK DIAGRAM Time based sequencing has the ability to turn supplies on in a specific order. However, it cannot guarantee that each supply has reached valid voltage levels before the next supply is sequenced on. Cascade sequencing guarantees the supplies are enabled a programmed period of time after the previous voltage has reached its minimum pro- grammed valid level. Figure 1 shows that each succeeding voltage must reach its minimum valid level before the timer is started to time the interval, t, for the next voltage. The duration of each t is programmable for each supply to supply transition. The next supply is not enabled until the timer has elapsed. See also Figure 5. Figure 1. Cascading Power Supplies CASCADE SEQUENCING 0V 4V 2V 6V T t t t 5V 2.5V 3.3V 1.8V 5V Valid 3.3V Valid 2.5V Valid 2047 Fig01 V + – REF NV DAC + – REF NV DAC + – REF NV DAC + – REF NV DAC V0 16 V1 2 V2 3 V3 14 MR# 1 PROGRAMMABLE WATCHDOG TIMER PROGRAMMABLE RESET PULSE GENERATOR SERIAL BUS CONTROL LOGIC 4K-BIT NV MEMORY RESET# PUP#1 11 5 4 SDA VDD_CAP WLDI 9 15 10 PUP#2 PUP#3 13 SCL A2 7 6 A1 CONFIGURATION REGISTER CONFIGURATION REGISTER GND 8 PROGRAMMABLE POWER CASCADING VDD_CAP 50k Ω 50k Ω 12 SUPPLY ARBITRATION V3 V2 V1 V0 VDD_CAP |
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