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SMM105NNCR05 데이터시트(PDF) 8 Page - Summit Microelectronics, Inc. |
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SMM105NNCR05 데이터시트(HTML) 8 Page - Summit Microelectronics, Inc. |
8 / 21 page SMM105 Preliminary Information Summit Microelectronics, Inc 2068 1.8 09/20/05 8 APPLICATIONS INFORMATION DEVICE OPERATION POWER SUPPLY The SMM105 can be powered by either an 8V to 15V input through the 12VIN pin or by a 2.7V to 5.5V input through the VDD pin (Figure 5). The 12VIN pin feeds an internal programmable regulator that internally generates either 5.5V or 3.6V. The internal regulator must be set to 3.6V if using an 8V supply. A voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the VDD input. This voltage arbitration circuit continuously checks for these voltages to determine which will power the SMM105. The resultant internal power supply rail is connected to the VDD_CAP pin that allows both filtering and hold-up of the internal power supply. VOLTAGE REFERENCE The SMM105 can operate using either an internal or external voltage reference, VREF. The internal VREF is set to 1.25V. Total accuracy with a ±0.1% external reference is ±0.2% and ±0.5% using the internal reference. MODES OF OPERATION The SMM105 has two basic modes of operation: UV and OV monitoring mode and supply margining mode ,and one key feature, Active DC Output Control (ADOC TM). A detailed description of each mode and feature follows. ACTIVE DC OUTPUT CONTROL (ADOC TM) The SMM105 can control the DC output voltage of bricks or DC/DC converters that have a trim pin. The TRIM pin on the SMM105 is connected to the trim input pin on the power supply converter. A sense line from the channel’s point-of-load connects to the VM input. The Active DC Control function cycles every 1.7ms making slight adjustments to the voltage on the TRIM output pin based on the voltage input on the VM pin. This voltage adjustment allows the SMM105 to control the output voltage of the power supply converter to within ±0.2% when using a ±0.1% external voltage reference. The voltage on the TRIM_CAP pins is buffered and applied to the TRIM pin. The voltage adjustments on the TRIM pin cause a slight ripple of less than 1mV on the power supply voltage. The amplitude of this ripple is a function of the TRIM_CAP capacitor and the trim gain of the converter. Calculation of the TRIM_CAP capacitor to achieve a desired minimum ripple is detailed in Application Note 37. The device can be programmed to either enable or disable the ADOC function. When disabled or not active, the TRIM pin on the SMM105 is a high impedance input. The voltage on the TRIM pin is buffered and applied to the TRIM_CAP pin charging the capacitor. This allows a smooth transition from the converter’s nominal voltage to the SMM105 controlling that voltage to the ADOC nominal setting. There are programmable Start times, TSTART, which are used to delay the ADOC function to allow the controlled supply to turn fully on before changing the output voltage level. There is also a programmable Speed-Up Convergence option. This option decreases the time required to bring a supply voltage from the converter’s nominal output voltage to the Active DC Output Control nominal voltage setting. MONITORING The SMM105 monitors the COMP1 and COMP2 inputs as well as the VM pin. COMP1 and COMP2 are high impedance inputs, each connected internally to a comparator and compared against the VREF_CNTL input. Each comparator can be independently programmed to monitor for either UV or OV. The monitor level is set externally with a resistive voltage divider. The part can be programmed to trigger the FAULT# pin when either COMPx comparator has exceeded the UV or OV range. The READY and FAULT# outputs of the SMM105 are active as long as the triggering limit remains in a fault condition. The READY pin is programmable active high/low open drain output indicates that VM is at its’ set point. When programmed as an active high output, READY can also be used as an input. When pulled low, it will latch the state of the comparator inputs. When either of the COMP1 or COMP2 inputs are in fault, the open- drain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is margining mode. |
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