9

2083 1.1 06/04/04

SMS46

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

Table 5. Configuration Register 6 (D3 through D7)

Note 1 - Read Only bit D7 is set to a 1. Read only bits

D4 and D3 are revision control and the value indi-

cates the status code of the device (ie. 01 is status

code 1).

Table 4. Status Register 5 (D4 through D7)

Table 3. Configuration Register 5 (D0 through D3)

If WLDI is held low the timer will free-run generating a series

timer is reset to time zero. Register 6 is also used to set

Table 6. Configuration Register 6 (D0, D1, D2)

n

o

i

t

c

A

3

D

B

S

M

2

D1

D

0

D

B

S

L

V

3

V

2

V

1

V

0

s

e

l

b

a

n

e

0

a

g

n

i

t

i

r

W

r

o

f

n

o

i

t

c

e

t

e

d

e

g

a

t

l

o

v

r

e

d

n

u

t

u

p

n

i

V

d

e

t

c

e

l

e

s

e

h

t

0000

s

e

l

b

a

n

e

1

a

g

n

i

t

i

r

W

r

o

f

n

o

i

t

c

e

t

e

d

e

g

a

t

l

o

v

r

e

v

o

t

u

p

n

i

V

d

e

t

c

e

l

e

s

e

h

t

1111

2

D1

D

0

D

B

S

L

n

o

i

t

c

A2

D

W1

D

W0

D

W

F

F

O

000

s

m

0

0

40

1

1

s

m

0

0

81

0

0

s

m

0

0

6

11

0

1

s

m

0

0

2

31

1

0

s

m

0

0

4

6

111

7

D

B

S

M

6

D5

D4

D3

D

d

a

e

R

1

y

l

n

O

1

O

T

R0

O

T

R

d

a

e

R

y

l

n

O

d

a

e

R

y

l

n

O

n

o

i

t

c

A

10

0

xx

t

O

T

R

P

s

m

5

2

=

10

1

xx

t

O

T

R

P

s

m

0

5

=

11

0

xx

t

O

T

R

P

s

m

0

0

1

=

11

1

xx

t

O

T

R

P

s

m

0

0

2

=

Table 7. Configuration Register 7 (D7, D6) Bits D5

through D0 are not used.

7

D

B

S

M

6

D

n

o

i

t

c

A

s

s

e

r

d

d

A

t

c

e

l

e

S

k

c

o

L0

S

A

x

0

n

e

h

w

y

l

n

o

s

d

n

o

p

s

e

r

,

0

1

0

1

=

I

T

D

s

e

t

a

t

s

c

i

g

o

l

1

A

&

2

A

=

s

t

i

b

s

s

e

r

d

d

a

x

1

n

e

h

w

y

l

n

o

s

d

n

o

p

s

e

r

,

1

1

0

1

=

I

T

D

s

e

t

a

t

s

c

i

g

o

l

1

A

&

2

A

=

s

t

i

b

s

s

e

r

d

d

a

0

xd

e

l

b

a

n

e

e

t

i

r

W

/

d

a

e

R

.

g

e

R

.

g

i

f

n

o

C

1

xt

u

o

d

e

k

c

o

l

e

t

i

r

W

/

d

a

e

R

.

g

e

R

.

g

i

f

n

o

C

Note 1 - Setting this bit will cause a permanent Read/Write Lock out.

1

7

D

B

S

M

6

D5

D

4

D

B

S

L

n

o

i

t

c

A

V

3

V

2

V

1

V

0

0000

e

h

t

s

e

t

a

c

i

d

n

i

1

a

g

n

i

d

a

e

R

t

l

u

a

f

t

i

m

il

f

o

t

u

o

f

o

e

c

r

u

o

s

1111

DEVICE OPERATION AND CONFIGURATION REGISTERS (CONTINUED)