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SMS47GR02 데이터시트(PDF) 10 Page - Summit Microelectronics, Inc. |
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SMS47GR02 데이터시트(HTML) 10 Page - Summit Microelectronics, Inc. |
10 / 19 page 10 SMS47 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. Preliminary Information Table 2. Configuration Register 4 CONFIGURATION REGISTERS SUPPLY AND MONITOR FUNCTIONS The V0, V1, V2, and V3 inputs are internally diode-ORed so that any one of the four can act as the device supply. The RESET# output will be guaranteed true so long as one of the four pins is at or above 1V. Note: for performing a Read or Write to the con- figuration register contents, at least one supply input must be above 2.7V. Read/Write operations require a 0.1µF capacitor from the VDD_CAP node to GND. For optimum performance connect capacitors from each of the Vx inputs to GND. Locate the capacitors as physically close to the SMS47 as possible. If cascading is enabled, the designer must insure V0 is the primary supply and is the first to become active. Associated with each input is a comparator with a program- mable threshold for detection of under-voltage or over- voltage conditions on any of the four supply inputs. The threshold can be programmed in 5mV increments any- where within the range of 0.6V to 1.875V or 15mV incre- ments within the range of 1.8V to 5.625V. Configuration registers 0, 1, 2, and 3 adjust the thresholds for V0, V1, V2, and V3 respectively. If the value contained in any register is all zeroes, the corresponding threshold will be 0.6V. If the contents were low range 05HEX the threshold would then be 0.625V [0.6V + (5 × 0.005V)]. All four registers are configured as 8-Bit registers. Table 1. Configuration Registers 0, 1, 2, and 3 RESET FUNCTION AND THRESHOLD RANGE The reset output has four programmable sources for activation. Configuration register 4 is used for selecting the activation source (D7:4), which can be any combination of V0, V1, V2 and V3. A monitor input can be programmed to activate on either an under-voltage or over-voltage condi- tion. The low-order four bits of configuration register 5 program these options. The reset threshold voltage range for V0 to V3 can be set for 5mV increments below 1.875V (low Range = "0") or for 15mV increments above 1.8V (high range = "1") using Bits D3:0. The RESET# output will become active when triggered by a selected activation source such as an under-voltage condition on V1. When this condition ceases, the RESET# output will remain active for tPRTO (programmable reset time-out). This reset time-out interval takes priority over the PUP outputs for use of the timer. The RESET# output has two hardwired sources for activa- tion: the MR# input, and the expiration of the Watchdog timer. RESET# will remain active so long as MR# is low, and will continue driving the RESET# output for tPRTO (programmable reset time out) after MR# returns high. The MR# input cannot be bypassed or disabled. Refer to Figures 2, 3 and 4 for a detailed illustration of the relationships among the affected signals. The status of the four supplies is available at any time over the I2C bus in the high order configuration bits of register 5 (Table 3). A "1" in a bit location indicates a fault on that supply. 7 D B S M 6 D5 D4 D3 D2 D1 D 0 D B S L n o i t c A 1 1 1111 1 1 V 5 2 6 . 5 = t n e m t s u j d a d l o h s e r h t t s e h g i H ) e g n a R h g i H ( 0 0 0000 0 0 V 6 . 0 = t n e m t s u j d a d l o h s e r h t t s e w o L ) e g n a R w o L ( 0 0 000 1 1 0 6 ( + V 6 . 0 = d l o h s e r h T × V 5 2 6 . 0 = ) V 5 0 0 . 0 ) . g . e ( 7 D B S M 6 D5 D4 D3 D2 D1 D 0 D B S L n o i t c A XXXX V 3 V 2 V 1 V 0 e l b a n E r e g g i r T T E S E R e g n a R d l o h s e r h T e g a tl o V t c e l e S 0000 w o L e g n a R 1111 h g i H e g n a R |
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