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TC58NVG1S3BFT00 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TC58NVG1S3BFT00
์ƒ์„ธ๋‚ด์šฉ  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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TC58NVG1S3BFT00 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Toshiba Semiconductor

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TC58NVG1S3BFT00/TC58NVG1S8BFT00
2003-10-30A
6
AC TEST CONDITIONS
CONDITION
PARAMETER
2.7 V
โ‰ค VCC โ‰ค 3.6 V
Input level
2.4 V, 0.4 V
Input pulse rise and fall time
3ns
Input comparison level
1.5 V, 1.5 V
Output data comparison level
1.5 V, 1.5 V
Output load
CL (100 pF) + 1 TTL
Note:
Busy to ready time depends on the pull-up resistor tied to the
BY
/
RY
pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta
= 0 to 70โ„ƒ, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NOTES
tPROG
Average Programming Time
๏ฃง
200
500
ยตs
N
Number of Partial Program Cycles in the Same Page
๏ฃง
๏ฃง
8
(1)
tBERASE
Block Erasing Time
๏ฃง
1.5
3
ms
(1) Refer to Application Note (12) toward the end of this document.


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