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TC58NVG1S3BFT00 데이터시트(PDF) 28 Page - Toshiba Semiconductor

부품명 TC58NVG1S3BFT00
상세설명  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TC58NVG1S3BFT00 데이터시트(HTML) 28 Page - Toshiba Semiconductor

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TC58NVG1S3BFT00/TC58NVG1S8BFT00
2003-10-30A
28
APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power
on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.
(2)
Power-on Reset
The device goes into automatic self initialization during power on if PSL is tied either to GND or NC.
During the initialization process, the device consumes a maximum current of 30 mA (ICCO0). If PSL is tied
to VCC, the device will not complete its self initialization during power on and will not consume ICCO0, and
completes the initialization process with the first Reset command input after power on. During the first FFh
reset Busy period, the device consumes a maximum current of 30 mA (ICCO0). In either case (PSL = GND/
NC or VCC), the following sequence is necessary because some input signals may not be stable at power-on.
(3)
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4)
Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h and FFh.
VIL
Operation
0 V
VCC
2.7 V
2.5 V
VIL
Don’t
care
Don’t
care
VIH
CE , WE , RE
WP
CLE, ALE
Invalid
Don’t
care
Ready/Busy
1 ms max
100
µs max
FF
Reset
Power on


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