GENNUM CORPORATION

52234 - 4

7

95

FOEN

Non-

synchronous

Input

Control Signal Input.

Used to enable or disable the FIFO status

flags. When FOEN is low, the FIFO status flags are enabled.

When FOEN is high, the FIFO status flags are disabled.

96

FFRST

Synchronous

wrt PCLK_IN

Input

Control Signal Input.

FFRST is used to supply synchronous

reset signals to the FIFO. When FFRST is low, the FIFO is reset

and all internal read and write address pointers are set to their

starting locations.

97

WEN

Synchronous

wrt W_CLK

Input

Control Signal Input.

Used to enable or disable writing to the

internal FIFO. When WEN is high, writing to the internal FIFO is

not allowed. Internal write address pointers are stopped at their

current position. WEN is sampled on the rising edge of W_CLK.

When WEN is low, writing to the FIFO is enabled.

98

REN

Synchronous

wrt PCLK_IN

Input

Control Signal Input.

Used to enable or disable incrementation

of the internal read address pointers. When REN is low, the

internal read address pointers are incremented with each clock

pulse. When REN is high, the internal read address pointers are

stopped at their current position.

100

FM_I/E

Non-

synchronous

Input

Control Signal Input.

When FM_I/E is high, the device operates

in a mode where the FIFO reset and read enable signals are

generated internally. In this mode, the device limits the data

insertion to the HANC region of the video stream. The ANC data

to be inserted into the current HANC region are externally

supplied via the FIFO interface during the active video period of

the previous line using the WEN signal. When FM_I/E is low, the

device operates in another mode where the FIFO reset and

read enable signals are generated externally by the user and

supplied to the device via the FFRST and REN control signal

inputs.

101

ANC_Y/C

Synchronous

wrt W_CLK

Input

Control Signal Input.

Used to control insertion of ANC data into

the LUMA or CHROMA FIFO. When ANC_Y/C is high, data

written to the device is placed into the internal LUMA FIFO, or

read into the Luma data stream. When ANC_Y/C is low, data

written to the device is placed into the internal CHROMA FIFO,

or read into the Chroma data stream.

103,104,105,

106, 107, 108,

111, 112, 113,

114

DATA_IN [19:10]

(LUMA channel)

Synchronous

wrt PCLK_IN

Input

Input Data Bus.

LUMA CHANNEL. DATA_IN [19] is the MSB of

the LUMA input signal (pin 103). DATA_IN [10] is the LSB of the

LUMA input signal (pin 114).

117, 118, 119,

120, 121, 122,

123, 124, 125,

126

DATA_IN [9:0]

(CHROMA channel)

Synchronous

wrt PCLK_IN

Input

CHROMA Input Data Bus.

CHROMA CHANNEL DATA_IN [9] is

the MSB of the CHROMA signal (pin 117). DATA_IN [0] is the

LSB of the CHROMA signal (pin 126).

1.2 PIN DESCRIPTIONS

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PIN NUMBER

NAME

TIMING

TYPE

DESCRIPTION