SI2109 datasheet(7/80 Pages) SILABS

부품명	SI2109

상세설명	SATELLITE RECEIVER FOR DVB-S/DSS

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제조업체	SILABS [Silicon Laboratories]

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Si2107/08/09/10

Preliminary Rev. 0.7

7

Figure 1. I2C Timing Diagram

Table 7. I2C Bus Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCL Clock Frequency

fSCL

0

—

400

kHz

Bus Free Time between START and

STOP Condition

tBUF

1.3

—

µs

Hold Time (repeated) START Condition.

(After this period, the first clock pulse is

generated.)

tHD, STA

0.6

—

µs

LOW Period of SCL Clock

tLOW

1.3

—

µs

HIGH Period of SCL Clock

tHIGH

0.6

—

µs

Data Setup Time

tSU, DAT

100

—

ns

Data Hold Time

tHD, DAT

0—

0.9

µs

SCL and SDA Rise and Fall Time

tr, tf

—

300

ns

Setup Time for a Repeated START Con-

dition

tSU, STA

0.6

—

µs

Setup Time for STOP Condition

tSU,STO

0.6

—

µs

Capacitive Load for each Bus Line

CB

—

400

pF

SDA

SCL

t

f

S

t

LOW

t

HD;STA

t

r

t

HIGH

t

SU;DAT

t

f

t

HD;DAT

t

SU;STA

S

r

t

SP

t

HD;STA

t

SU;STO

t

BUF

t

r

PS

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Silicon Laboratories	SI2109	1Mb / 94P	SATELLITE RECEIVER FOR DVB-S/DSS WITH QUICKLOCK AND QUICKSCAN
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SI2109 데이터시트(PDF) 7 Page - Silicon Laboratories

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