전자부품 데이터시트 검색엔진 |
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SI3200-KS 데이터시트(PDF) 9 Page - Silicon Laboratories |
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SI3200-KS 데이터시트(HTML) 9 Page - Silicon Laboratories |
9 / 128 page Si3232 Preliminary Rev. 0.96 9 Noise Performance Idle Channel Noise4 C-Message weighted — 12 15 dBrnC Psophometric weighted — –78 –75 dBmP 3 kHz flat — — 18 dBrn PSRR from VDD1 – VDD4 RX and TX, dc to 3.4 kHz 40 — — dB PSRR from VBAT RX and TX, dc to 3.4 kHz 60 — — dB Longitudinal Performance Longitudinal to Metallic Bal- ance (forward or reverse) 200 Hz to 1 kHz 58 63 — dB 1 kHz to 3.4 kHz 53 58 — dB Metallic to Longitudinal Bal- ance 200 Hz to 3.4 kHz 40 — — dB Longitudinal Impedance5 200 Hz to 3.4 kHz at TIP or RING Register-dependent OBIAS/ABIAS 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA — — — — 50 25 25 20 — — — — Ω Ω Ω Ω Longitudinal Current per Pin5 Active off-hook 200Hz to 3.4kHz Register-dependent OBIAS/ABIAS 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA — — — — 4 8 8 10 — — — — mA mA mA mA Table 4. AC Characteristics (Continued) (VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade) Parameter Test Condition Min Typ Max Unit Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 3. VDD = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register coefficients. 4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz will not exceed –55 dBm. 5. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off- hook active conditions, respectively. This per-pin total current setting should be selected such that it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application. |
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