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TSC87C52-12IAR 데이터시트(PDF) 4 Page - TEMIC Semiconductors |
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TSC87C52-12IAR 데이터시트(HTML) 4 Page - TEMIC Semiconductors |
4 / 24 page TSC87C52 4 Rev. C – 10 Sept 1997 Preliminary MATRA MHS Pin Description VSS Circuit ground potential. VSS1 Secondary ground (not on DIP). Provided to reduce ground bounce and improve power supply by–passing. Note: This pin is not a substitute for the VSS pin. Connection is not necessary for proper operation. VCC Supply voltage during normal, Idle, and Power Down operation. Port 0 Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1’s. Port 0 can sink eight LS TTL inputs. Port 0 is used as data bus during EPROM programming and program verification. Port 1 Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, in the DC parameters section) because of the internal pullups. Port 1 can sink/ source three LS TTL inputs. It can drive CMOS inputs without external pullups. Port1 also serves the functions of the following special features of the TSC87C52 as listed below: Port Pin Alternate Function P1.0 P1.1 T2 (External Count input to Timer/Counter 2), Clock–Out T2EX (Timer/Counter 2 Capture/Reload Trigger and direction Control) Port 1 receives the low–order address byte during EPROM programming and program verification. Port 2 Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL, in the DC parameters section) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Port 2 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups. Some Port 2 pins receive the high–order address bits and control signals during EPROM programming and program verification. Port 3 Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL, in the DC parameters section) because of the pullups. |
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