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CX51191 데이터시트(PDF) 4 Page - List of Unclassifed Manufacturers

부품명 CX51191
상세설명  0.18um Structured ASIC
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CX51191 데이터시트(HTML) 4 Page - List of Unclassifed Manufacturers

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CX5000:
0.18um Structured ASIC Product Family
© ChipX Inc.
4
CEC034 (9/20/05)
The memories can be surrounded by a BIST shell for convenient and comprehensive production testing.
The number of permutations and combinations of memory options prevents easy distribution of pre-
defined macros, therefore, ChipX maintains an automatic memory macro generation utility that can email
memory models automatically upon request. For instructions on how to use this feature, please check the
CX5000 Design Manual.
Corner
Figure 2 (next page) illustrates the CX5000 die corner that contains a number of important analog
components. Each corner contains an accurate bandgap device, which is then used to provide reference
and bias voltages to other components in the pad ring. Also contained in each corner is a complete,
programmable analog PLL.
The PLL may be configured to operate at frequencies between 7.5MHz and 500MHz given certain input
clock criterion and loop filter choices. ChipX provides an automatic response server that will reply with
simulation and synthesis macros for a specific frequency PLL based on the input frequency, desired
output frequency, and phase relationship. The PLL models may be easily disabled and bypassed to
reduce simulation time.
ChipX CX5000 logic is fast when compared to standard FPGA logic, so it is possible to create all of the
counters, dividers, and clock phase taps from synthesized logic rather than relying on custom macros.
The corner also contains an ESD structure that is used in concert with the ESD structures adjacent to the
pads to provide 2.5KV of ESD protection to the devices.
Figure 1. CX5000 CX-Memory Configurations
SRAM Cell Array
1 or 2 Memory Instances
256 Addresses x 64 Bits
Up To 11
Metal Programmable
Address Decoder A
Metal Programmable
Address Decoder B
Up To 11
4 To 64
4 To 64
4-64
4-64
32
32
R/W
R/W
256
256
1, Dual Port SRAM
2, Single Port RAM/ROMs
Metal programmable
Interconnect
Port A
Port B


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