10 / 13 page
FM25W256
Rev. 1.0
Aug. 2004
Page 10 of 13
AC Parameters (TA = -40°C to + 85°C, CL = 30pF)
VDD 2.7 to 3.3V
VDD 3.3 to 5.5V
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
fCK
SCK Clock Frequency
0
20
0
25
MHz
tCH
Clock High Time
22
18
ns
1
tCL
Clock Low Time
22
18
ns
1
tCSU
Chip Select Setup
10
10
ns
tCSH
Chip Select Hold
10
10
ns
tOD
Output Disable Time
20
15
ns
2
tODV
Output Data Valid Time
22
15
ns
tOH
Output Hold Time
0
0
ns
tD
Deselect Time
60
60
ns
tR
Data In Rise Time
50
50
ns
1,3
tF
Data In Fall Time
50
50
ns
1,3
tSU
Data Setup Time
5
5
ns
tH
Data Hold Time
5
5
ns
tHS
/Hold Setup Time
10
10
ns
tHH
/Hold Hold Time
10
10
ns
tHZ
/Hold Low to Hi-Z
20
20
ns
2
tLZ
/Hold High to Data Active
20
15
ns
2
Notes
1.
tCH + tCL = 1/fCK.
2.
This parameter is characterized but not 100% tested.
3.
Rise and fall times measured between 10% and 90% of waveform.
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V)
Symbol
Parameter
Min
Max
Units
Notes
tPU
Power Up (VDD min) to First Access (/CS low)
10
-
ms
tVR
VDD Rise Time
50
µs/V
1,2
tVF
VDD Fall Time
100
-
µs/V
1,2
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol
Parameter
Min
Max
Units
Notes
CO
Output capacitance (SO)
-
8
pF
1
CI
Input capacitance
-
6
pF
1
Notes
1.
This parameter is characterized and not 100% tested.
2.
Slope measured at any point on VDD waveform.
Data Retention (VDD = 2.7V to 5.5V)
Parameter
Min
Max
Units
Notes
Data Retention
10
-
Years
AC Test Conditions
Input Pulse Levels
10% and 90% of VDD
Input rise and fall times
5 ns
Input and output timing levels
0.5 VDD
Equivalent AC Load Circuit
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