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GS880F32BT-5.5IV 데이터시트(PDF) 7 Page - GSI Technology

부품명 GS880F32BT-5.5IV
상세설명  512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
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GS880F32BT-5.5IV 데이터시트(HTML) 7 Page - GSI Technology

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Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
GS880F18/32/36BT-xxxV
Rev: 1.00 6/2006
7/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above table.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18


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