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GS8161FZ36BD-5.5 데이터시트(PDF) 11 Page - GSI Technology |
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GS8161FZ36BD-5.5 데이터시트(HTML) 11 Page - GSI Technology |
11 / 28 page GS8161FZ18/32/36BD Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.00 6/2006 11/28 © 2006, GSI Technology Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tZZR tZZH tZZS tKL tKL tKH tKH tKC tKC CK ZZ |
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