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GS8160F32T-6I 데이터시트(PDF) 7 Page - GSI Technology

부품명 GS8160F32T-6I
상세설명  1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
Logo GSI - GSI Technology

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GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.12 11/2004
7/22
© 1999, GSI Technology
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in
the above tables.
Burst Counter Sequences
BPR 1999.05.18
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
HHHH
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
LLLLL
2, 3, 4
Write all bytes
L
XXXX
X
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00


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