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GS8170DW72C-200I 데이터시트(PDF) 8 Page - GSI Technology |
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GS8170DW72C-200I 데이터시트(HTML) 8 Page - GSI Technology |
8 / 27 page GS8170DW36/72C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.04 5/2005 8/27 © 2002, GSI Technology, Inc. Special Functions Burst Cycles Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. SigmaRAM Pipelined Burst Reads with Counter Wraparound Read A Cont A+1 Cont A+2 Cont A+3 Cont A Deselect A Q(A) Q(A+1) Q(A+2) Q(A+3) Q(A) CK Address ADV E1 W DQA0–DQA8 CQ ADV Counter Wraps D1 D2 D0 /E1 /W CQ DQ D2 D3 Write Continue XX Internal Address A2 A3 A0 A1 A2 CK Address A2 XX Continue Continue Continue XX XX XX SigmaRAM Double Late Write SRAM Burst Writes with Counter Wrap-around |
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